Image sensing device and image sensing system

ABSTRACT

An image sensing device comprises: a pixel array that is arrayed such that pixels that output signals to column signal lines constitute a plurality of rows and a plurality of columns, and in which the plurality of pixels are connected to each of the plurality of column signal lines; a plurality of readout units that read out signals from the pixel array via the plurality of column signal lines, each of the plurality of readout units including an input transistor that receives a signal that has been read out via the column signal line; and a first load transistor that supplies an electric current to the input transistor, and a plurality of first bias supply units that supply mutually different bias voltages to gates of the first load transistors at least in readout units of the plurality of readout units and arranged adjacent to each other.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to image sensing devices and image sensingsystems.

2. Description of the Related Art

An image sensing device comprises a pixel array in which a plurality ofpixels are arrayed in a direction along rows and a direction alongcolumns. A line noise which extends in a horizontal direction(hereinafter referred to as “horizontal line noise”) sometimes occurs inimages captured by image sensing devices.

Specifically, horizontal line noise sometimes occurs due to a generationmechanism shown in Japanese Patent Laid-Open No. 2006-128704. As shownin FIG. 2 of Japanese Patent Laid-Open No. 2006-128704, parasiticoverlap capacitances CP(0) to CP(m) are formed between gates of loadtransistors ML(0) to ML(m) and column analog buses Bus (0) to Bus(m).When a data voltage is read out after a reset voltage has been read outfrom the pixels to the column analog buses Bus(0) to Bus(m) to carry outCDS processing, the voltages of the column analog buses Bus(0) to Bus(m)change from the reset voltage to the data voltage. This change involtage affects the bias voltages via the overlap capacitances CP(0) toCP(m). The bias voltages are transmitted from an active transistor MF tothe load transistors ML(0) to ML(m). In this way, the gate voltages ofthe load transistors ML(0) to ML(m) fluctuate, and therefore theelectric currents that flow in the column analog buses Bus(0) to Bus(m)also fluctuate. Due to this fluctuation in bias voltages, proper valuesare not achieved for image signals, which are a difference between thereset voltages and the data voltages when capturing a bright subject,and this is a cause of horizontal line noise. That is, the more drasticthe fluctuations in the voltages of the column analog buses become, thatis, the brighter the brightness of a subject become, the more drasticthe fluctuations in bias voltages become so that horizontal line noiseincreases.

In respect to these issues, Japanese Patent Laid-Open No. 2006-128704proposes increasing the driving force of the active transistors MF byincreasing their size and electric current, and stabilizing the biasvoltages. In this way, horizontal line noise can be decreased accordingto Japanese Patent Laid-Open No. 2006-128704.

It should be noted that in the technique shown in Japanese PatentLaid-Open No. 2006-128704, the sizes of the load transistors ML(0) toML(m) are kept the same as conventional sizes. According to JapanesePatent Laid-Open No. 2006-128704, this is to suppress decrease in thedynamic range of the pixels due to increased electric currents of theanalog buses.

However, horizontal line noise is sometimes not decreased even whenusing the technique shown in Japanese Patent Laid-Open No. 2006-128704.For example, even when using the technique shown in Japanese PatentLaid-Open No. 2006-128704, horizontal line noise is still sometimesconspicuous in images obtained by capturing an object at dark times orby capturing extremely dark objects.

Specifically, horizontal line noise sometimes occurs due to a separategeneration mechanism that is not described in Japanese Patent Laid-OpenNo. 2006-128704. As shown in FIG. 2 of Japanese Patent Laid-Open No.2006-128704, when an interface state is present in a gate insulatingfilm of the active transistors MF, that interface state captures andreleases electrons and positive holes that form an electric currentIbias flowing in a channel, and therefore fluctuation (flicker noise)occurs in that electric current Ibias. This fluctuation in the electriccurrent Ibias affects bias voltages that are transmitted from the activetransistors MF to the load transistors ML(0) to ML(m). In this way, thegate voltages of the load transistors ML(0) to ML(m) fluctuate, andtherefore electric currents Ibias*x that flow to the column analog busesBus(0) to Bus(m) also fluctuate. In response to this, the values of thereset voltages and data voltages that are read out from the pixels tothe column analog buses Bus(0) to Bus(m) fluctuate undesirably. Due tothis fluctuation in bias voltages, proper values (substantially zero)are not achieved for image signals, which are a difference between thereset voltages and the data voltages when a subject is captured in astate close to no signal, that is, when capturing an object at a darktime or capturing an extremely dark object, and this is a cause ofhorizontal line noise.

SUMMARY OF THE INVENTION

The present invention provides for suppressing horizontal line noise inan image obtained by capturing an object at a dark time or by capturinga dark object.

An image sensing device according to a first aspect of the presentinvention comprising: a pixel array that is arrayed such that pixelsthat output signals to column signal lines constitute a plurality ofrows and a plurality of columns, and in which the plurality of pixelsare connected to each of the plurality of column signal lines; aplurality of readout units that read out signals from the pixel arrayvia the plurality of column signal lines, each of the plurality ofreadout units including an input transistor that receives a signal thathas been read out via the column signal line; and a first loadtransistor that supplies an electric current to the input transistor,and a plurality of first bias supply units that supply mutuallydifferent bias voltages to gates of the first load transistors at leastin readout units of the plurality of readout units and arranged adjacentto each other.

An image sensing system according to a second aspect of the presentinvention comprising: the image sensing device according to the firstaspect of the present invention; an optical system in which an image isformed on an imaging surface of the image sensing device, and a signalprocessing unit that processes signals output from the image sensingdevice to generate image data.

With the present invention, it is possible to suppress horizontal linenoise in an image obtained by capturing an object at a dark time or bycapturing a dark object.

Further features of the present invention will become apparent from thefollowing description of exemplary embodiments with reference to theattached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a configuration diagram of an image sensing device 100according to a first embodiment.

FIG. 2 is a timing chart showing an operation of the image sensingdevice 100.

FIG. 3 is a configuration diagram of a column amplifier 113.

FIG. 4 is a configuration diagram of an image sensing device 100 iaccording to a modified example of the first embodiment.

FIG. 5 is a configuration diagram of an image sensing system in which aphotoelectric conversion device according to the first embodiment isapplied.

FIG. 6 is a configuration diagram of an image sensing device 100according to the first embodiment.

FIG. 7 is a configuration diagram of an image sensing device 500according to a second embodiment.

FIG. 8 is a configuration diagram of an image sensing device 600according to a third embodiment.

FIG. 9 is a configuration diagram of an image sensing device 700according to a fourth embodiment.

DESCRIPTION OF THE EMBODIMENTS

The description regarding an image sensing device 100 according to afirst embodiment of the present invention is given using FIG. 1.

The image sensing device 100 comprises a pixel array PA, a verticalscanning circuit 126, a plurality of column readout circuits (readoutcircuit) 111 a and 111 b, a horizontal scanning circuit 128, and amirror transistor 118. The image sensing device 100 further comprises aplurality of mirror transistors (plurality of bias supply units) 110 aand 110 b, and a plurality of load transistors (plurality of loadtransistors) 109 a and 109 b.

In the pixel array PA, pixels are arrayed so as to constitute aplurality of rows and a plurality of columns. In order to simplifydescription, FIG. 1 illustrates a case where the pixel array PA isconstituted by two rows and three columns, but in an actual imagesensing device, the number of pixels contained in the pixel array PA ismuch greater (see FIG. 6). A plurality of column signal lines 107 a and107 b, which extend to a lower side (side of one end) of the pixel arrayPA in FIG. 1, are connected to pixels of odd numbered columns (a portionof the columns) in the pixel array PA. A plurality of pixels areconnected to each of the plurality of column signal lines 107 a and 107b. A column signal line 140 a, which extends to an upper side (side ofother end) of the pixel array PA in FIG. 1, is connected to pixels ofeven numbered columns (a portion of the columns) in the pixel array PA.A plurality of pixels are connected to the column signal line 140 a.When the number of columns in the pixel array PA is four or more, aplurality of column signal lines extending to the upper side of thepixel array PA is provided in a same manner as the column signal line140 a (as shown in FIG. 6).

The vertical scanning circuit 126 scans the pixel array PA in a verticaldirection (direction along the columns). The vertical scanning circuit126 selects and drives the pixels of each row by supplying controlsignals to the pixels of each row via control lines. The control signalsinclude reset signals PRES(n+1) and PRES(n) and transfer signalsPTX(n+1) and PTX(n).

Connected to the column signal lines 107 a and 107 b (107 a to 107 pshown in FIG. 6), which extend to the lower side of the pixel array PA,are the respectively corresponding load transistors 109 a and 109 b andthe column readout circuits (first readout unit group) 111 a and 111 b.Similarly, connected to the plurality of column signal lines 140 a andso on (140 a to 140 p shown in FIG. 6), which extend to the upper sideof the pixel array PA, are a plurality of load transistors (not shown indrawings) and a plurality of column readout circuits (second readoutunit group, not shown in drawings). Furthermore, mirror transistors (notshown in drawings) are connected to the plurality of load transistorsand the plurality of column readout circuits respectively.

The plurality of column readout circuits 111 a and 111 b read outsignals from the pixels of columns connected via the column signal lines107 a and 107 b respectively. The plurality of column readout circuits111 a and 111 b correspond to the plurality of odd numbered columns(first column and third column) in the pixel array PA.

The horizontal scanning circuit 128 scans the plurality of columnreadout circuits 111 a and 111 b in a horizontal direction. Thehorizontal scanning circuit 128 successively selects the column readoutcircuits 111 a and 111 b of each of the odd numbered columns andsuccessively transfers the signals (S signal and N signal) read out fromthe pixels of each of the odd numbered columns to an output amplifier133. The output amplifier 133 generates and outputs image signals bycarrying out a CDS process in which a difference between the S signaland the N signal is obtained.

The mirror transistor 118 is short-circuited between the gate and thedrain. The gate of the mirror transistor 118 is connected to theplurality of column readout circuits 111 a and 111 b.

Each of the plurality of mirror transistors 110 a and 110 b isshort-circuited between the gate and the drain. The plurality of mirrortransistors 110 a and 110 b supply a bias voltage to the loadtransistors 109 a and 109 b. In FIG. 1, one load transistor 109 a isconnected to the mirror transistor 110 a, but when the presentembodiment is applied to a pixel array having a much greater number ofcolumns, a plurality of load transistors may be connected to a singlemirror transistor. However, note that at least load transistors arrangedadjacent to each other are connected to different mirror transistors.The plurality of load transistors 109 a and 109 b are connected to eachof the plurality of column signal lines 107 a and 107 b and determinethe electric current that flows to the column signal lines 107 a and 107b. For example, the drains of the plurality of load transistors 109 aand 109 b are connected to the column signal lines 107 a and 107 brespectively and their sources are connected to a ground electricpotential.

The mirror transistor 110 a and the load transistor 109 a form a currentmirror circuit. In this way, the load transistor 109 a enables anelectric current corresponding to a drain electric current Ibias1 a ofthe mirror transistor 110 a to flow in the column signal line 107 a.Furthermore, the mirror transistor 110 b and the load transistor 109 bform a current mirror circuit. In this way, the load transistor 109 benables a drain electric current corresponding to a drain electriccurrent Ibias1 b of the mirror transistor 110 b to flow to the columnsignal line 107 b.

Here, the gate of the mirror transistor 110 a is connected to the gateof the load transistor 109 a that is connected to the column signal line107 a. And the gate of the mirror transistor 110 b is connected to thegate of the load transistor 109 b that is connected to the column signalline 107 b. That is, the gates of at least the load transistors 109 aand 109 b arranged adjacent to each other of the plurality of loadtransistors 109 a and 109 b are connected to the gates of mutuallydifferent mirror transistors of the plurality of mirror transistors 110a and 110 b. In this way, the plurality of mirror transistors 110 a and110 b supply mutually different bias voltages to the gates of at leastload transistors arranged adjacent to each other of the plurality ofload transistors 109 a and 109 b. For this reason, the electric currentsdetermined by the load transistors 109 a and 109 b arranged adjacent toeach other can suppress fluctuation in a similar manner. As a result,even if an effect of electric current fluctuation as described above (orbias voltage fluctuation) appears in an image corresponding to imagesignals output via the column signal lines 107 a and 107 b, it ispossible to ensure that the effect of the electric current fluctuationin that image is not conspicuous. That is, it is possible to suppresshorizontal line noise in an image obtained by capturing an object at adark time or by capturing a dark object.

The description of a configuration of each pixel in the pixel array PAis given using FIG. 1. Hereinafter, the configuration of a pixel P11 isdescribed as an example, but the configurations of other pixels areequivalent to the configuration of the pixel P11.

The pixel P11 includes a photoelectric conversion unit 102, a transferunit 103, a charge-voltage converter 104, an amplification transistor105, and a reset unit 106.

The photoelectric conversion unit 102 generates an electric chargecorresponding to light. The photoelectric conversion unit 102 is, forexample, a photodiode.

The transfer unit 103 transfers the electric charge generated by thephotoelectric conversion unit 102 to the charge-voltage converter 104.The transfer unit 103 is, for example, a transfer transistor and itturns on when an active transfer signal PTX(n) is supplied to its gatesuch that the electric charge generated by the photoelectric conversionunit 102 is transferred to the charge-voltage converter 104.

The charge-voltage converter 104 converts the transferred electriccharge to a voltage. The charge-voltage converter 104 also functions asan input unit of the amplification transistor 105. The charge-voltageconverter 104 is, for example, a floating diffusion region.

By working as a source follower together with the load transistor 109 a,the amplification transistor 105 (amplifies and) outputs a signalcorresponding to the voltage of the charge-voltage converter 104 to thecolumn signal line 107 a. A power voltage VD is supplied to the drain ofthe amplification transistor 105 via a power supply line 108.

The reset unit 106 resets the charge-voltage converter 104. The resetunit 106 is, for example, a reset transistor and it turns on when anactive reset signal PRES(n) is supplied to its gate so as to reset thecharge-voltage converter 104. A power voltage VD is supplied to thedrain of the reset unit (reset transistor) 106 via the power supply line108.

The description of a configuration of the column readout circuits 111 aand 111 b is given using FIG. 1. Hereinafter, the configuration of thecolumn readout circuit 111 a is described as an example, but theconfigurations of other column readout circuits are equivalent to theconfiguration of the column readout circuit 111 a.

The column readout circuit 111 a includes a column amplifier circuit(amplifier circuit) 112 and a holding circuit 130.

The column amplification circuit 112 includes a column amplifier 113, aninput capacitor 114, a feedback capacitor 115, a clamp control switch116, and a bias input terminal 117. A reference signal VREF is input toa non-inverting input terminal 124 of the column amplifier 113, and theinput capacitor 114 is connected to an inverting input terminal 125thereof. Furthermore, the feedback capacitor 115 and the clamp controlswitch 116 are connected in parallel to the inverting input terminal 125and an output terminal 123 of the column amplifier 113. The gate of themirror transistor 118 is connected to the bias input terminal 117 of thecolumn amplifier 113.

The holding circuit 130 includes transfer switches 119 n and 119 s,storage capacitors 120 n and 120 s, and transfer switches 121 n and 121s. By turning on/off the transfer switch 119 n, the output terminal 123of the column amplifier 113 and the storage capacitor 120 n areconnected/disconnected. By turning on/off the transfer switch 119 s, theoutput terminal 123 of the column amplifier 113 and the storagecapacitor 120 s are connected/disconnected. By turning on/off thetransfer switch 121 n, the storage capacitor 120 n and an output line122 n are connected/disconnected. By turning on/off the transfer switch121 s, the storage capacitor 120 s and an output line 122 s areconnected/disconnected.

The description of a configuration of the column amplifier 113 is givenusing FIG. 3. FIG. 3 is a configuration diagram of the column amplifier113. Hereinafter, the configuration of the column amplifier 113contained in the column readout circuit 111 a is described as anexample, but the configurations of other column amplifiers contained inthe column readout circuits are equivalent to the configuration of thecolumn amplifier 113 contained in the column readout circuit 111 a.

The column amplifier 113 is, for example, a differential amplifiercircuit in which N-channel type MOS transistors are used as inputtransistors. The column amplifier 113 includes input transistors 301 and302, a load transistor 303, and transistors 304 and 305.

The input transistor 301 is an N-channel type MOS transistor, and itsgate is connected to a non-inverting input terminal 124 (see FIG. 1).The input transistor 302 receives a reference signal VREF. The inputtransistor 302 is an N-channel type MOS transistor, and its gate isconnected to an inverting input terminal 125 (see FIG. 1) and its drainis connected to the output terminal 123 (see FIG. 1). The inputtransistor 302 receives signals that have been read out via the columnsignal line 107 a.

The gate of the load transistor 303 is connected to the bias inputterminal 117 (see FIG. 1). The load transistor 303 determines theelectric current that flows through the input transistors 301 and 302corresponding to the bias voltage supplied to its gate via the biasinput terminal 117. The load transistor 303 enables an electric currentcorresponding to a drain electric current Ibias2 of the mirrortransistor 118 to flow through the input transistors 301 and 302.

Here, the back-gates of the input transistors 301 and 302 and the loadtransistor 303 are connected to a GND electric potential via commonwiring.

A transistor 304 is a P-channel type MOS transistor, and isshort-circuited between its gate and drain. A transistor 305 is aP-channel type MOS transistor. The transistor 304 and the transistor 305form a current mirror circuit. The back-gates of the transistor 304 and305 are connected to a power source VDD.

The description of an operation of the image sensing device 100 is givenusing FIG. 2. FIG. 2 is a timing chart showing an operation of the imagesensing device 100. Hereinafter, although the description is centered onan operation relating to pixels of odd numbered columns in the pixelarray PA, an operation relating to pixels of even numbered columns isalso the similar.

Row selection operations in the image sensing device 100 according tothe present embodiment are carried out by controlling a gate electricpotential of the amplification transistor 105 of FIG. 1. For example,row selection operations are carried out by lowering the gate electricpotential of the amplification transistor 105 of non-selected rows andraising the gate electric potential of the amplification transistor 105of selected rows.

The column signal line 107 a serves as an output node of a sourcefollower circuit formed by the amplification transistor 105 and the loadtransistor 109 a of the selected rows. The gate of the load transistor109 a is connected to the gate and the drain of the mirror transistor110 a, and an electric current in accordance with the electric currentIbias1 a that flows through the mirror transistor 110 a flows in thecolumn signal line 107 a.

The column signal line 107 b serves as an output node of a sourcefollower circuit formed by the amplification transistors 105 of theselected rows and the load transistor 109 b. The gate of the loadtransistor 109 b is connected to the gate and the drain of the mirrortransistor 110 b, and an electric current in accordance with theelectric current Ibias1 b that flows through the mirror transistor 110 bflows in the column signal line 107 b.

The amplification transistor 105 of the selected rows is activated andthe amplification transistors 105 of the non-selected rows isdeactivated, and therefore the column signal lines 107 a and 107 b aregiven an electric potential in accordance with the electric potential ofthe charge-voltage converter 104 of the selected rows.

In a first part of a pixel readout period RT1(n) shown in FIG. 2, thereset signal PRES(n) and PRES(n+1) of all the rows are high due tocontrol of the vertical scanning circuit 126. At this time, thecharge-voltage converters 104 of all pixels are reset to a low level viathe power supply line 108 and the reset unit (reset transistor) 106 ofeach of the pixels P11. An electric potential level VD of the powersupply line 108 at this time is in low level.

In a second part of the pixel readout period RT1(n), the reset signalPRES(n+1) of rows excluding the selected row (n-th row) becomes lowlevel. After this, the electric potential level VD of the power supplyline 108 becomes high level, and then the charge-voltage converters 104of the selected row are reset to a high level. Further still, the resetsignal PRES(n) becomes low level. At this time, a noise signalcorresponding to a state in which the charge-voltage converter 104 hasbeen reset is read out to the column signal line 107 a.

While the noise signal corresponding to a state in which thecharge-voltage converter 104 has been reset is read out to the columnsignal line 107 a, a signal PCLMP becomes high level. In this way, theinverting input terminal 125 and the output terminal 123 of the columnamplifier 113 are short-circuited, and the output terminal 123 isclamped at the VREF electric potential. The output signal of the columnamplifier 113 at this time is read out to the storage capacitor 120 nvia the transfer switch 119 n by setting the signal PTN to high level.The output signal that is read out at this point is handled as an Nsignal. The N signal is a signal in which the offset of the columnamplifier 113 is included. After this, the transfer unit (transfertransistor) 103 is turned on for a predetermined period by a transferpulse PTX(n) (e.g. PTX(1)), and the charge-voltage converter 104converts the transferred charge to a voltage. The amplificationtransistor 105 outputs a signal (optical signal) corresponding to thevoltage of the charge-voltage converter 104 to the column signal line107. At this time, the signal PCLMP is low, and a signal which isobtained by reducing, from the optical signal, the noise signalcomponent corresponding to the state in which the charge-voltageconverter 104 has been reset, is input to the column amplifier 113. Thecolumn amplifier 113 generates an S signal in which a voltage component,to which an inverse gain has been applied with respect to thenoise-reduced optical signal, is superimposed on the N signal (offset ofthe column amp). Following this, the signal PTS becomes high, and the Ssignal corresponding to the optical signal is read out to the storagecapacitor 120 s via the transfer switch 119 s.

A horizontal transfer operation is carried out in a horizontal scanningperiod HT1(n). That is, the N signals and S signals of columns selectedby the horizontal scanning circuit 128 are transferred sequentially fromthe column readout circuits 111 a and 111 b of each column to the outputlines 122 n and 122 s. The output amplifier 133 generates and outputs animage signal of a pixel on the n-th row, in which the offset of thecolumn amplifier has been removed, by carrying out CDS processing inwhich a difference between the transferred N signal and S signal isobtained.

By sequentially scanning the rows selected by the vertical scanningcircuit 126 and repeating the above-described pixel readout operation,image signals of all the pixels in the pixel array PA are generated andoutput.

As described above, in the present embodiment, two mirror transistors110 a and 110 b are provided. The two mirror transistors are alternatelyconnected to the load transistors connected to the pixel output linesthat are read out on an upper side (or lower side). There is differentfluctuation in electric current due to the flicker noise that occurs inthe mirror transistors 110 a and 110 b. In this way, the effect ofelectric current fluctuation (bias voltage fluctuation) of the mirrortransistors 110 a and 110 b can be caused to vary between signalstransmitted by column signal lines that are adjacent to each other. Thatis, the signals of pixels adjacent to each other in odd numbered columns(or even numbered columns) have different fluctuation effects andhorizontal line noise is greatly reduced. As a result, horizontal linenoise when capturing an object at a dark time or capturing extremelydark objects is greatly reduced and it becomes possible to obtain anexcellent image. Furthermore, by applying the present invention to asingle-panel color image sensing device, even higher quality imagecapturing can be carried out.

It should be noted that an example was shown in which the two mirrortransistors 110 a and 110 b were provided, but a greater effect can beobtained by providing a greater number of mirror transistors. However,there is a tradeoff with, for example, the increase of power consumptionby increasing the number of Ibias1 a and Ibias1 b, or the increase ofthe chip size along with the complexity of layouts.

Furthermore, in an image sensing device 100 i, the column signal linesmay extend to only one side with respect to the pixel array PA as shownin FIG. 4. In this case, a gate of a load transistor 149 ai, which isconnected to a column signal line 140 ai connected to pixels of evennumbered columns, is connected to a gate of the mirror transistor 110 b.Furthermore, gates of the load transistors 109 a and 109 bi, which areconnected to the column signal lines 107 a and 107 b connected to pixelsof odd numbered columns, are connected to a gate of the mirrortransistor 111 a.

FIG. 5 shows an example of an image sensing system in which an imagesensing device according to the present invention has been applied.

As shown in FIG. 5, an image sensing system 90 mainly comprises anoptical system, the image sensing device 100, and a signal processingunit. The optical system mainly comprises a shutter 91, a lens 92, and astop 93. The signal processing unit mainly comprises an sensed signalprocessing circuit 95, an A/D converter 96, an image signal processingunit 97, a memory unit 87, an external I/F unit 89, a timing generationunit 98, an overall control and arithmetic unit 99, a recording medium88, and a recording medium control I/F unit 94. It should be noted thatthe signal processing unit does not necessarily comprise the recordingmedium 88.

The shutter 91 is arranged on an optical path in front of the lens 92and controls the exposure.

The lens 92 refracts light that has entered to form an image of anobject on the pixel array (imaging surface) of the image sensing device100.

The stop 93 is arranged on the optical path between the lens 92 and theimage sensing device 100, and adjusts an amount of light that is guidedto the image sensing device 100 after passing through the lens 92.

The image sensing device 100 converts the image of the object formed onthe pixel array to image signals. The image sensing device 100 reads outthe image signals from the pixel array and outputs the image signals.

The sensed signal processing circuit 95 is connected to the imagesensing device 100 and processes the image signals that are output fromthe image sensing device 100.

The A/D converter 96 is connected to the sensed signal processingcircuit 95, and converts the image signals (analog signals) that havebeen output after processing from the sensed signal processing circuit95 to digital signals.

The image signal processing unit 97 is connected to the A/D converter96, and carries out arithmetic processing such as various kinds ofcorrections on the image signals (digital signals) output from the A/Dconverter 96 to generate image data. This image data is supplied to thememory unit 87, the external I/F unit 89, the overall control andarithmetic unit 99, the recording medium control I/F unit 94, and thelike.

The memory unit 87 is connected to the image signal processing unit 97,and stores image data that has been output from the image signalprocessing unit 97.

The external I/F unit 89 is connected to the image signal processingunit 97. In this way, image data that has been output from the imagesignal processing unit 97 is transferred to external devices (personalcomputers and the like) via the external I/F unit 89.

The timing generation unit 98 is connected to the image sensing device100, the sensed signal processing circuit 95, the A/D converter 96, andthe image signal processing unit 97. In this way, timing signals aresupplied to the image sensing device 100, the sensed signal processingcircuit 95, the A/D converter 96, and the image signal processing unit97. And the image sensing device 100, the sensed signal processingcircuit 95, the A/D converter 96, and the image signal processing unit97 operate in synchronization with the timing signals.

The overall control and arithmetic unit 99 is connected to the timinggeneration unit 98, the image signal processing unit 97, and therecording medium control I/F unit 94, and performs overall control ofthe timing generation unit 98, the image signal processing unit 97, andthe recording medium control I/F unit 94.

The recording medium 88 is detachably connected to the recording mediumcontrol I/F unit 94. In this way, image data that has been output fromthe image signal processing unit 97 is recorded to the recording medium88 via the recording medium control I/F unit 94.

With this configuration, excellent images (image data) can be obtainedif excellent image signals can be obtained by the image sensing device100.

The description regarding an image sensing device 500 according to asecond embodiment of the present invention is given using FIG. 7. FIG. 7is a configuration diagram of the image sensing device 500 according tothe second embodiment of the present invention.

Although the fundamental configuration of the image sensing device 500is similar to the first embodiment, the image sensing device 500 isdifferent from that of the first embodiment in the following points. Theimage sensing device 500 comprises a plurality of load transistors 509 ato 509 p, a plurality of column readout circuits 511 a to 511 p, amirror transistor 510, and a plurality of mirror transistors 518 a and518 b.

Each of the gates of the load transistors 509 a to 509 p is connected tothe gate of the mirror transistor 510.

The two mirror transistors 518 a and 518 b are alternately connected tothe column readout circuits 511 a to 511 p connected to the columnsignal lines 107 a to 107 p extending to a lower side of the pixel arrayPA. That is, the gates (bias input terminals 517) of the loadtransistors 303 inside at least the column readout circuits arrangedadjacent to each other in the plurality of column readout circuits 511 ato 511 p are connected to the gates of mutually different mirrortransistors. For example, the load transistor 303 (see FIG. 3) of thecolumn readout circuit 511 a determines an electric currentcorresponding to a drain electric current Ibias2 a of the mirrortransistor 518 a that is to flow through the input transistors 301 and302. Furthermore, for example, the load transistor 303 of the columnreadout circuit 511 b determines an electric current corresponding to adrain electric current Ibias2 b of the mirror transistor 518 b that isto flow through the input transistors 301 and 302 (see FIG. 3). In thisway, the electric currents determined by the load transistors 303arranged adjacent to each other can suppress fluctuation in a similarmanner. As a result, even if an effect of electric current fluctuationappears in an image corresponding to image signals output via the columnsignal lines 107 a and 107 b, it is possible to ensure that the effectof the electric current fluctuation in that image is not conspicuous. Inother words, it is possible to suppress horizontal line noise in animage obtained by capturing an object at a dark time or by capturing adark object.

It should be noted that the second embodiment can achieve a large effectwhen noises originating in the mirror transistors connected to thecolumn readout circuits 511 a to 511 p is larger than noises originatingin the mirror transistors connected to the load transistors 509 a to 509p.

The description regarding an image sensing device 600 according to athird embodiment of the present invention is given using FIG. 8. FIG. 8is a configuration diagram of the image sensing device 600 according tothe third embodiment of the present invention.

Although the fundamental configuration of the image sensing device 600is similar to the first embodiment, the image sensing device 600 isdifferent from that of the first embodiment in the following points. Theimage sensing device 600 comprises a plurality of column readoutcircuits 611 a to 611 p and a plurality of mirror transistors (aplurality of first bias supply units) 618 a and 618 b.

Each of the plurality of column readout circuits 611 a to 611 p includesa load transistor (first load transistor) 303. The two mirrortransistors 618 a and 618 b are alternately connected to the columnreadout circuits 611 a to 611 p respectively connected to the columnsignal lines 107 a to 107 p extending to a lower side of the pixel arrayPA. That is, the gates (bias input terminals 617) of at least the loadtransistors 303 arranged adjacent to each other of the plurality of loadtransistors 303 are connected to the gates of mutually different mirrortransistors of the plurality of mirror transistors 618 a and 618 b. Inthis way, it is possible to suppress fluctuating of the electriccurrents determined by the load transistors 303 inside the columnreadout circuits arranged adjacent to each other in a similar manner. Asa result, even if an effect of electric current fluctuation appears inan image corresponding to image signals output via the column signallines 107 a and 107 b, it is possible to make less conspicuous theeffect of the electric current fluctuation in an image. In other words,it is possible to suppress horizontal line noise in an image obtained bycapturing an object at a dark time or by capturing a dark object.

It should be noted that the third embodiment can achieve a large effectwhen noises originating in the mirror transistors connected to the loadtransistors 109 a to 109 p and noises originating in the mirrortransistors connected to the column readout circuits 611 a to 611 p areequivalent.

The description regarding an image sensing device 700 according to afourth embodiment of the present invention is given using FIG. 9. FIG. 9is a configuration diagram of the image sensing device 700 according tothe fourth embodiment of the present invention.

Although the fundamental configuration of the image sensing device 700is similar to the first embodiment, the image sensing device 700 isdifferent from that of the first embodiment in the following points. Theimage sensing device 700 is a single-chip color image sensing devicecommonly used in digital cameras and the like. The image sensing device700 comprises a pixel array PA700.

A plurality of pixels P11 to Pmn in the pixel array PA700 furtherinclude color filters CF11 to CFmn respectively. The color filters CF11to CFmn transmit light of some wavelength in a visible region so thatlight of that wavelength enters into the photoelectric conversion unit102.

In the image signals output from the image sensing device 700, an imagesignal of each pixel has information regarding only one type of color.Accordingly, as described in an example of Japanese Patent Laid-Open No.2000-287219, a color image in which all the colors (for example, RGB) ofall the pixels are available can be generated by performinginterpolation on image data corresponding to image signals output fromthe image sensing device using information (image data) of nearbypixels. In single-chip color image sensing devices, it is known that theeffect of horizontal line noise is accentuated since a certain pixelcontains information of nearby pixels.

For example, consider a case such as that shown in FIG. 9 in which anarray of the color filters CF11 to CFmn is formed in a Bayerarrangement. In reading out a row of B pixels and G2 pixels, the Bpixels are read out to the lower side and the G2 pixels are read out tothe upper side. In this case, the flicker noise generated in the lowerside mirror transistors affects all the B pixel signals and the upperside affects all the G2 pixel signals. Consequently, although horizontalline noise affects every other pixel, by performing interpolationprocessing using the information of nearby pixels are described above,there is a possiblity that the horizontal line noise component of the Bpixels for example can be accentuated in the G2 pixels also.

Even in this case, according to the present embodiment, the colorfilters in the plurality of pixels in which signals are read out in asame period by column readout circuits among the plurality of columnreadout circuits 111 a to 111 p and arranged adjacent to each othertransmit light of a same wavelength range (same color). For example, acolor filter CF11 of the pixel P11 and a color filter CF13 of the pixelP13 transmit light of a wavelength corresponding to the same color (B).And the gates of at least the load transistors 109 a and 109 b arrangedadjacent to each other in the plurality of load transistors 109 a and109 b are connected to the gates of mutually different mirrortransistors of the plurality of mirror transistors 110 a and 110 b. Inthis way, it is possible to suppress fluctuation of the electriccurrents determined by the load transistors 109 a and 109 b arrangedadjacent to each other in a similar manner. As a result, the effects ofelectric current fluctuation may vary between the B pixels P11 and P13to the left and right of the G2 pixel P12 for example, and therefore thehorizontal line noise in the G2 pixel P12 can be reduced by performinginterpolation processing using information of nearby pixels. As aresult, even when interpolation processing is carried out usinginformation of nearby pixels, it is possible to suppress horizontal linenoise in an image obtained by capturing an object at a dark time or bycapturing a dark object. Accordingly, it is possible to improve imagequality.

While the present invention has been described with reference toexemplary embodiments, it is to be understood that the invention is notlimited to the disclosed exemplary embodiments. The scope of thefollowing claims is to be accorded the broadest interpretation so as toencompass all such modifications and equivalent structures andfunctions.

This application claims the benefit of Japanese Patent Application No.2008-148326, filed Jun. 5, 2008, which is hereby incorporated byreference herein in its entirety.

1.-6. (canceled)
 7. An image sensing device comprising: a pixel arrayhaving a plurality of pixels which form rows and columns, wherein eachpixel is connected to one of a plurality of column signal lines; aplurality of load transistors, each connected to one of the plurality ofcolumn signal lines; a readout circuit that reads out signals from thepixel array, via column signal lines, of the plurality of column signallines, to which one of the plurality of load transistors is connected;and a plurality of bias supply units, wherein load transistors, of theplurality of load transistors, which are arranged adjacent to eachother, are biased by different bias supply units of the plurality ofbias supply units.
 8. The image sensing device according to claim 7,wherein the load transistors and the bias supply units that are mutuallyconnected form current mirror circuits.
 9. The image sensing deviceaccording to claim 7, wherein the readout circuit is arranged at a firstside of the pixel array so as to read out signals from pixels of a partof the plurality of column signal lines, and wherein the device furthercomprises: a plurality of second load transistors, each connected to oneof the plurality of column signal lines, to which none of the pluralityof load transistors is connected; a second readout circuit that isarranged at a second side of the pixel array and reads out signals fromthe pixel array, via column signal lines, of the plurality of columnsignal lines, to which respective load transistors of the plurality ofsecond load transistors are connected; and a plurality of second biassupply units, wherein second load transistors, of the plurality ofsecond load transistors, which are arranged adjacent to each other, arebiased by different second bias supply units of the plurality of secondbias supply units.
 10. The image sensing device according to claim 9,wherein each pixel in the pixel array includes a photoelectricconversion unit and a color filter, and wherein pixels from whichsignals are read out by the readout circuit in a same period thoroughthe column signal lines, to which the load transistors arranged adjacentto each other are connected, have a same color, and pixels from whichsignals are read out by the second readout circuit in a same periodthorough the column signal lines, to which the second load transistorsarranged adjacent to each other are connected, have a same color.
 11. Animage sensing system comprising: an image sensing device according toclaim 7; an optical system in which an image is formed on an imagingsurface of the image sensing device; and a signal processing unit thatprocesses signals output from the image sensing device to generate imagedata.